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ADT7490
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(T A = T MIN to T MAX , V CC = V MIN to V MAX , unless otherwise noted) (Note 1)
Parameter
Conditions
Min
Typ
Max
Unit
Digital Input Logic Levels (TACH1 to TACH3)
Input High Voltage, V IH
Input Low Voltage, V IL
Hysteresis
Maximum Input Voltage
Minimum Input Voltage
2.0
?
?
? 0.3
?
?
?
?
?
0.5
?
5.5
0.8
?
?
V
V
V p-p
Digital Input Logic Levels (THERM)
Input High Voltage, V IH
Input Low Voltage, V IL
0.75 ? V CCP
?
?
?
?
0.4
V
V
Digital Input Current
Input High Current, I IH
Input Low Current, I IL
Input Capacitance, C IN
V IN = V CC
V IN = 0
?
?
?
? 1
? 1
5.0
?
?
?
m A
m A
pF
Serial Bus Timing (Note 2) (See Figure 2)
Clock Frequency, f SCLK
Glitch Immunity, t SW
Bus Free Time, t BUF
SCL Low Time, t LOW
SCL High Time, t HIGH
SCL, SDA Rise Time, t r
SCL, SDA Fall Time, t f
Data Setup Time, t SU;DAT
10
?
4.7
4.7
4.0
?
?
250
?
?
?
?
?
?
?
?
400
50
?
?
50
1,000
300
?
kHz
ns
m s
m s
m s
ns
m s
ns
Detect Clock Low Timeout, t TIMEOUT
Can be Optionally Disabled
15
?
35
ms
1. All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are T A = 25 ? C and represent a parametric norm.
Logic inputs accept input high voltages up to V MAX , even when the device is operating down to V MIN . Timing specifications are tested at logic
levels of V IL = 0.8 V for a falling edge, and V IH = 2.0 V for a rising edge.
2. Guaranteed by design, not production tested.
3. V TT is the voltage input on Pin 8. The V TT voltage is determined by the processor installed on the system.
t LOW
t R
t F
t HD; STA
SCL
t HD; STA
t HD; DAT
t HIGH
t SU; DAT
t SU; STA
t SU; STO
SDA
P
t BUF
S
S
P
Figure 2. Serial Bus Timing Diagram
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